F. Boito, L. Teylo, M. Popov, T. Jolivel, F. Tessier, J. Luettgau, J. Monniot, A. Tarraf, A. R. Carneiro, and C. Osthoff. “A Deep Look Into the Temporal I/O Behavior of HPC Applications”. In: 2025 IEEE International Parallel and Distributed Processing Symposium (IPDPS). Milano, Italy, June 2025 (accepted)(link)
S. Pernice, A. Tarraf, J.-B. Besnard, B. Cantalupo, D. E. Singh, A. C. Garcia, F. Wolf, S. Shende, J. Carretero, and M. Aldinucci. “A Simulation-Based Framework to Reduce I/O Contention in HPC”. In: 2025 IEEE International Parallel and Distributed Processing Symposium (IPDPS). Milano, Italy, June 2025, pp. 1–2 (accepted)
A. Tarraf, J. F. Muñoz, D. E. Singh, T. Özden, J. Carretero, and F. Wolf, “I/O Behind the Scenes: Bandwidth Requirements of HPC Applications With Asynchronous I/O,” in 2024 IEEE International Conference on Cluster Computing (CLUSTER), Kobe, Japan, Sep. 2024 (IEEE).
A. Tarraf, et al., “Malleability in modern HPC systems: Current experiences, challenges, and future opportunities,” IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 6, pp. 1–14, Jun. 2024, doi: 10.1109/TPDS.2024.3406764 (IEEE)
A. Tarraf, A. Bandet, F. Boito, G. Pallez, and F. Wolf: Capturing Periodic I/O Using Frequency Techniques. In Proc. of the 38th IEEE International Parallel and Distributed Processing Symposium (IPDPS), San Francisco, CA, USA, pages 1–14, IEEE, May 2024.
J.-B. Besnard, A. Tarraf, A. Cascajo, and S. Shende, “Introducing the metric proxy for holistic I/O measurements,” in The 10th HPC I/O in the data center workshop (HPC-IODC’24), held in conjunction with the ISC high performance conference, Hamburg, Germany, May 2024.
J.-B. Besnard, A. Tarraf, C. Barthélemy, A. Cascajo, E. Jeannot, S. Shende, and F. Wolf, "Towards Smarter Schedulers: Molding Jobs into the Right Shape via Monitoring and Modeling", HPCMALL 2023 - 2nd international workshop on malleability techniques applications in high-performance computing, Hamburg, Germany, May 2023 (link)
M. Ritter, A. Tarraf, A. Geiß, N. Daoud, B. Mohr, and F. Wolf, "Conquering Noise With Hardware Counters on HPC Systems," In Proc. of the Workshop on Programming and Performance Visualization Tools (ProTools), held in conjunction with the Supercomputing Conference (SC22), pages 1-10, IEEE, 2022 (IEEE)
A. Tarraf and L. Hedrich,"Towards Compositional Abstraction of Analog Neuronal Networks", Computing and Communication Workshop and Conference (CCWC), Jan. 2021 (IEEE)
A. Tarraf, "Formal Abstraction and Verification of Analog Circuits", Universität Frankfurt a.M, 2021 (Dissertation)
A. Tarraf and L. Hedrich, "Analog Circuit Abstraction to SystemC-AMS Secured by Affine Forms", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Erlangen, Germany, July 2021 (IEEE)
A. Tarraf and L. Hedrich, "From Transistor Level to Cyber Physical/Hybrid Systems: Formal Verification Using Automatic Compositional Abstraction", IT - Information Technology (Journal)
A. Tarraf and L. Hedrich, "Modeling Circuits with Parameter Variation by ELSA: Eigenvalue Based Linear Hybrid System Abstraction", 17. GMM/ITG-Fachtagung ANALOG, 2020 (IEEE)
A. Tarraf, N. Kochdumper, M. Rechmal, L. Hedrich, and M. Olbrich, "Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets", In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020 (IEEE)
A. Tarraf and L.Hedrich, "Verification of modeling: metrics and methodologies", Modelling methodologies in analog integrated circuit design, G. Dündar and M. B. Yelten, Eds., Institution of Engineering & Technology, 2020, pp. 95-116 (Book)
N. Kochdumper, A. Tarraf, M. Rechmal, M. Olbrich, L. Hedrich, and M. Althoff, "Establishing Reachset Conformance for the Formal Analysis of Analog Circuits", ASP-DAC, 2020 (IEEE)
Ö. Erduran, M. Minor, A. Tarraf, L. Hedrich, F. Rühl, H. Schroth, "Multi-agent learning for energy-aware placement of autonomous vehicles", Int. Conf. on Machine Learning and Applications (ICMLA), Florida, USA, Dec. 2019 (IEEE)
A. Tarraf and L. Hedrich, "Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, July 2019 (IEEE)
A. Tarraf and L. Hedrich, "Behavioral Modeling of Transistor-Level Circuits Using Automatic Abstraction to Hybrid Automata", Design Automation and Test in Europe (DATE), Florence, Italy, 2019 (IEEE)
A. Tarraf and L. Hedrich, "Automatic Abstraction of Analog Circuits to Hybrid Automata", 16. GMM/ITG-Fachtagung Analog, Munich, Germany, 2018 (IEEE)
A. Tarraf and L. Hedrich, "Automatic Abstraction of Transistor Level Circuits to Hybrid Automata", Frontiers in Analog CAD (FAC), Vienna, Austria, 2018 (PDF)
T. Raste and A. Tarraf, "Flachheitsbasierte Trajektoriengenerierung und Folgeregelung mit modellprädiktiver und modellfreier Regelung", VDI/VDE Fachtagung AUTOREG, Berlin, 2017 (PDF)