2024
2024
I/O Behind the Scenes: Bandwidth Requirements of HPC Applications With Asynchronous I/O
IEEE Cluster 2024, Kobe, Japan, Sep 27, 2024 (link)
Expert Talk II: Unveiling I/O Insights of HPC Applications Using the Metric Proxy and FTIO
4th Workshop on Re-envisioning Extreme-Scale I/O for Emerging Hybrid HPC Workloads, Kobe, Japan, Sep 24, 2024 (link)
Frequency Techniques for I/O
17th Scheduling for large-scale systems workshop, Aussois, France, June 27, 2024 (link)
Capturing Periodic I/O Using Frequency Techniques
IPDPS'24, San Francisco, USA, May 29, 2024 (link)
Introducing the Metric Proxy for Holistic I/O Measurements
HPC-IODC Workshop held in conjunction with the ISC High Performance Conference, Hamburg, Germany, May 16, 2024 (link)
Frequency Techniques for I/O
HiPEAC, Munich, Germany, January 17, 2024 (link, abstract)
Frequency Techniques for I/O
ADMIRE User Day, Barcelona, Spain, December 12, 2023 (link)
Modeling I/O of HPC applications with Extra-P
ADMIRE User Day, Barcelona, Spain, December 12, 2023 (link)
Malleability workstream (cross-project group) presentation
Textarossa EuroHPC Collaboration Workshop, Turin, Italy, June 7, 2023 (link)
Optimization cycles workstream (DEEP-SEA group) presentation
Textarossa EuroHPC Collaboration Workshop, Turin, Italy, June 7, 2023 (link)
Detecting Periodic I/O Behavior Using Frequency Techniques
Teratec Forum, Paris, France, June 1, 2023 (link)
Conquering Noise With Hardware Counters on HPC Systems
NHR PerfLab Seminar, April 18, 2023, online (recording, link, slides)
Conquering Noise With Hardware Counters on HPC Systems
4th Workshop on Programming and Performance Visualization Tools, SC 22, Dallas, Texas, US, November 13, 2022 (slides)
Towards Compositional Abstraction of Analog Neuronal Networks
CCWC, Jan 2021 (online)
Modeling Circuits with Parameter Variation by ELSA: Eigenvalue Based Linear Hybrid System Abstraction
17. GMM/ITG-Fachtagung ANALOG, Sep. 2020 (online)
Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets
ISVLSI, July 2020 (online)
Automatic Modeling of Transistor Level Circuits by Hybrid Systems with Parameter Variable Matrices
SMACD, Lausanne, Switzerland, July 2019
Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata"
DATE, Florence, Italy, Mar 2019
Automatic Abstraction of Analog Circuits to Hybrid Automata
16. GMM/ITG-Fachtagung Analog, Munich, Germany, 2018
Automatic Abstraction of Transistor Level Circuits to Hybrid Automata
Frontiers in Analog CAD (FAC), Vienna, Austria, 2018 (slides)